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Sam Dietrich Good evening. I'm Sam Dietrich.

Kara Rousseau And I'm Kara Rousseau. Welcome to Simulectics Radio.

Sam Dietrich Tonight we're examining what happens when the instruction set architecture—the fundamental interface between hardware and software—becomes open and royalty-free. For decades, processor design has been dominated by proprietary ISAs controlled by a handful of companies. ARM licenses their architecture for a fee. Intel and AMD control x86 through patents and cross-licensing. This creates friction, licensing costs, and design constraints. RISC-V offers an alternative: an open ISA specification that anyone can implement without paying royalties. The question is whether openness at the ISA level changes the economics and innovation dynamics of processor design, or whether the real barriers lie elsewhere—in manufacturing, verification, and ecosystem development.

Kara Rousseau And what it means to decouple the interface specification from the implementation. Open source software succeeded because source code is the implementation—if you have the code, you can run it, modify it, redistribute it. But an ISA is just a specification. You still need to design the microarchitecture, build or access fabrication capacity, develop toolchains and operating systems. Openness removes one barrier, but does it remove the one that actually matters? We're exploring whether open hardware can follow the trajectory of open software, or whether the physics and economics of silicon impose different constraints.

Sam Dietrich To discuss both the technical foundations and strategic implications of RISC-V, we're joined by two of its principal architects. Dr. Krste Asanović is a Professor of Computer Science at UC Berkeley and co-founder of SiFive, a company commercializing RISC-V processors. Dr. David Patterson is also a Professor at Berkeley, a Turing Award laureate for his work on computer architecture, and a key figure in the development of RISC principles. Gentlemen, welcome.

Dr. Krste Asanović Thank you. Good to be here.

Dr. David Patterson Delighted to join you.

Kara Rousseau Let's start with the motivation. Why create a new ISA when established architectures already exist? What problem were you solving?

Dr. Krste Asanović We started RISC-V at Berkeley around 2010 because we needed a clean, modern ISA for research and education. Existing architectures had accumulated decades of legacy features, and the proprietary ones had licensing restrictions that made them unsuitable for open academic work. We wanted something simple, modular, and extensible—an ISA designed from scratch with the lessons of the past forty years. The goal was not to compete with ARM or x86 commercially, at least initially, but to create a platform for computer architecture research that could be freely shared.

Dr. David Patterson And simplicity matters. If you look at x86, it's carrying decades of backward compatibility constraints. The encoding is irregular, there are multiple instruction formats for historical reasons, and the architecture is extraordinarily complex to implement efficiently. ARM is cleaner, but it's still proprietary and has its own legacy. We wanted to apply RISC principles—simple instructions, regular encoding, orthogonal design—without compromise. The modularity is key: a minimal base ISA with optional extensions for specific needs. You don't pay for features you don't use, either in silicon area or design complexity.

Sam Dietrich Walk me through the base ISA. What's included in the minimal RISC-V specification?

Dr. Krste Asanović The base integer ISA, called RV32I or RV64I depending on whether you're targeting 32-bit or 64-bit address spaces, has about forty instructions. Integer arithmetic, logical operations, loads and stores, branches. Everything uses a consistent 32-bit instruction encoding with a small number of formats. There are thirty-two general-purpose registers. That's it. You can build a complete, functional processor with just that. Then there are standard extensions: M for integer multiply and divide, A for atomic instructions, F and D for single and double-precision floating point, C for compressed 16-bit instructions to improve code density. You pick the extensions you need.

Kara Rousseau The modularity is architecturally elegant, but doesn't it create fragmentation? If different implementations support different extensions, how do you ensure software portability?

Dr. David Patterson That's a legitimate concern, and it's something we've addressed through profiles. A profile is a standardized combination of base ISA and extensions that guarantees a certain level of functionality. For instance, the RVA profiles define what's required for running rich operating systems like Linux. If your processor conforms to a profile, software written for that profile will run. It's similar to how ARM has different profiles for application processors versus microcontrollers. The key is that the ISA specification is open, so there's no proprietary control over which combinations are blessed.

Sam Dietrich Let's talk about the ecosystem. An ISA is only useful if there are compilers, debuggers, operating systems, and libraries. How mature is the RISC-V software ecosystem compared to ARM or x86?

Dr. Krste Asanović It's maturing rapidly. The GCC and LLVM compilers have had RISC-V backends for years, and they're well-maintained. Linux has native RISC-V support in the mainline kernel. There are ports of FreeBSD, various embedded operating systems, and real-time OSes. The tooling is solid for bare-metal embedded development. Where we're still catching up is in the breadth of third-party software—commercial applications, proprietary drivers, things that have decades of accumulation on x86. But for embedded systems, IoT, and new application domains, RISC-V is competitive.

Kara Rousseau Embedded and IoT are significant markets, but they're not the high-margin server and client computing segments. Can RISC-V compete in data centers or laptops, or is it fundamentally suited to different niches?

Dr. David Patterson There's no fundamental reason RISC-V can't compete in any segment. The ISA itself is not the limiting factor. The challenges are ecosystem maturity, software compatibility, and the established positions of incumbents. Intel and AMD have decades of optimization in their microarchitectures and enormous software ecosystems. ARM has similar advantages in mobile. Displacing them requires not just a good ISA, but compelling performance, power efficiency, and a value proposition that justifies the switching cost. That said, we're seeing RISC-V processors targeting data center and HPC workloads. It's a longer play, but it's happening.

Sam Dietrich Let's talk about the business model. If the ISA is free, where's the value captured? How do companies make money in a RISC-V ecosystem?

Dr. Krste Asanović The ISA is just the interface. The value is in the implementation—the microarchitecture, the physical design, the integration, the IP blocks around the core. Companies like SiFive sell processor IP and chips. Others sell design services, verification tools, or development boards. The open ISA lowers the barrier to entry, which means more companies can design custom processors for specific applications without paying licensing fees. That creates a more competitive market, which is good for innovation and cost reduction. The value shifts from controlling the interface to delivering superior implementations.

Kara Rousseau That's a different value structure than the traditional model where ARM licenses the architecture and captures a percentage of every chip sold. Does the open model enable use cases that wouldn't exist under a licensing regime?

Dr. David Patterson Absolutely. Academic research, for one. Universities can design and simulate RISC-V processors without negotiating licenses. Open-source hardware projects can build actual chips using RISC-V cores without legal encumbrances. Companies in regions or industries that face export controls or IP restrictions can develop their own processors. And there's the domain-specific computing angle—if you're designing an accelerator for a specific workload, you can tightly couple it with a RISC-V core and extend the ISA as needed. You're not locked into someone else's roadmap.

Sam Dietrich Custom extensions are powerful but they also risk fragmenting the ISA. How do you balance extensibility with the need for a coherent ecosystem?

Dr. Krste Asanović The specification reserves opcode space for custom extensions, but they're clearly marked as non-standard. The expectation is that domain-specific extensions are for specialized accelerators or proprietary features, and they don't interfere with the standard ISA. For extensions that have broad applicability, there's a process to propose them for standardization through RISC-V International, the organization that governs the ISA. It's a balance between enabling innovation and maintaining compatibility.

Kara Rousseau Governance is interesting. RISC-V International is a non-profit organization where companies and universities collaborate on the ISA specification. How does that differ from proprietary development, and what are the risks?

Dr. David Patterson The open governance model means no single company controls the roadmap. Extensions are developed by working groups with diverse membership. The risk is that the process can be slower than a proprietary model where one company makes all the decisions. But the benefit is that the ISA evolves to meet the needs of a broad community rather than the strategic interests of a single vendor. That should lead to better technical decisions and avoid the kinds of lock-in that plague proprietary architectures.

Sam Dietrich Let's talk about verification and testing. One of the challenges of open hardware is ensuring correctness. With proprietary processors, the vendor is responsible for validation. In a RISC-V ecosystem where anyone can implement the ISA, how do you ensure implementations are correct?

Dr. Krste Asanović RISC-V International maintains a compliance test suite that implementations can run to verify they conform to the specification. It's not exhaustive—there's no test suite that can catch every bug—but it covers the ISA semantics. Beyond that, individual companies are responsible for their own verification. The open specification actually helps here, because it's unambiguous and publicly reviewed. With proprietary ISAs, you sometimes see discrepancies between the official documentation and the actual behavior of processors, which creates compatibility issues. Openness means the spec is the ground truth.

Kara Rousseau But does openness lead to a proliferation of low-quality implementations? If the barrier to entry is lower, do we end up with more processors that claim RISC-V compliance but have subtle bugs or performance problems?

Dr. David Patterson That's possible, but it's a feature, not a bug. Lowering the barrier to entry means more experimentation, which leads to innovation. Some implementations will be low-quality, and they'll fail in the market. Others will be excellent and gain traction. The open model accelerates the evolutionary process. Compare this to the current situation where only a handful of companies can afford to design processors. More diversity, more competition, faster learning.

Sam Dietrich What about the physical layer—manufacturing? You can design a RISC-V processor, but if you can't fabricate it economically, the openness of the ISA doesn't help. How does RISC-V address the fab access problem?

Dr. Krste Asanović It doesn't, directly. Fab access is orthogonal to the ISA. But the open ISA does enable more foundries and fabs to support RISC-V without negotiating exclusive deals. We've seen RISC-V chips fabbed at TSMC, Samsung, GlobalFoundries, and others. There are also initiatives like shuttle runs and MPW services that let smaller companies and academic groups get silicon at lower cost. The ISA being open means any foundry can support it without restrictions.

Kara Rousseau Let's consider the counterfactual. If RISC-V hadn't been created, what would be different? Would we just have ARM everywhere, or would something else have emerged?

Dr. David Patterson I think we'd see more fragmentation and proprietary extensions. Companies frustrated with ARM licensing would create their own ISAs, and we'd have even less software portability than we do now. RISC-V provides a neutral meeting ground. Instead of every company reinventing the wheel, they can collaborate on the ISA and compete on implementation. That's more efficient, both technically and economically.

Sam Dietrich Looking forward, where does RISC-V go from here? What are the next technical challenges and strategic opportunities?

Dr. Krste Asanović Vector processing is a big area. We have the RISC-V Vector Extension, which is designed to be scalable across different implementations. That's important for AI workloads, scientific computing, multimedia. There's also work on virtualization, security extensions, and advanced memory models. On the strategic side, RISC-V is gaining traction in China, India, and Europe as a way to reduce dependence on US-controlled architectures. That geopolitical dimension is significant.

Kara Rousseau The geopolitical angle is interesting and concerning. If RISC-V becomes a way to circumvent export controls or build computing infrastructure outside Western supply chains, does that create tension with the open, collaborative ethos of the project?

Dr. David Patterson It's a tension that exists in any open technology. You can't control how people use an open standard. But I'd argue that having a neutral, internationally governed ISA is better than a world where every geopolitical bloc develops proprietary architectures. RISC-V International is based in Switzerland precisely to avoid being subject to any single country's export controls. The goal is to keep the ISA open and available globally, even as individual implementations and companies navigate their own regulatory environments.

Sam Dietrich Dr. Asanović, Dr. Patterson, this has been a fascinating discussion. Thank you for your time and for your work on RISC-V.

Dr. Krste Asanović Thank you.

Dr. David Patterson Our pleasure.

Kara Rousseau That's our program for tonight. Until tomorrow, remember that openness at the interface doesn't guarantee openness at every layer.

Sam Dietrich And that the real innovation often happens in the implementation, not the specification. Good night.